A VLSI design of new memory reduction turbo code decoder

Tsung Han Tsai; Cheng Hung Lin

A VLSI design of new memory reduction turbo code decoder

Tsung Han Tsai, Cheng Hung Lin

電機工程學系

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm², clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.

原文	???core.languages.en_GB???
頁面	249-252
頁數	4
出版狀態	已出版 - 2005
事件	9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA - Hsinchu, Taiwan 持續時間: 28 5月 2005 → 30 5月 2005

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???event.eventtypes.event.conference???	9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA
國家/地區	Taiwan
城市	Hsinchu
期間	28/05/05 → 30/05/05

引用此

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abstract = "In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm2, clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.",

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AB - In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm2, clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.

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A VLSI design of new memory reduction turbo code decoder

摘要

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