A vlsi architecture design for dual-mode qam and vsb digital catv transceiver

Muh Tian Shiue, Chorng Kuang Wang, Winston Ingshih Way

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions [1], [2]. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10bit ADC input signal SNR is 36dB, and there are ±6kHz of carrier frequency offset, ±110 ppm of symbol rate offset, and -82 dBc carrier phasejitter at 10 kHz away from the nominal carrier frequency. key words: QAM, VSB, AGC, carrier recovery, timing recovery, fractionally spaced blind equalizer and DFE.

原文???core.languages.en_GB???
頁(從 - 到)2351-2356
頁數6
期刊IEICE Transactions on Communications
E81-B
發行號12
出版狀態已出版 - 1998

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