@inproceedings{7092af6b89f6440aa10c1054699923fb,
title = "A variable duty cycle with high-resolution synchronous mirror delay",
abstract = "A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD. Fine locking is achieved by the phase shifter for the sake of fast locking. Measure results show that the maximum clock skew of the proposed SMD is 33.64ps in the frequency range from 200 to 450MHz and that the consumption power is 9.71mW at 450MHz in a 0.18-μm 1P6M N-well CMOS process at 1.8V power supply. The total locking time is less than 10 clock cycles.",
author = "Hong, {Kai Wei} and Lee, {Chien Hsien} and Cheng, {Kuo Hsing} and Wu, {Chen Lung} and Yang, {Wei Bin}",
year = "2006",
doi = "10.1109/ICECS.2006.379852",
language = "???core.languages.en_GB???",
isbn = "1424403952",
series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
pages = "569--572",
booktitle = "ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems",
note = "ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems ; Conference date: 10-12-2006 Through 13-12-2006",
}