A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

Yen Liang Yeh, Xiang Lin, Hong Yeh Chang, Kevin Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

5 引文 斯高帕斯(Scopus)

摘要

A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.

原文???core.languages.en_GB???
主出版物標題RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509012350
DOIs
出版狀態已出版 - 27 9月 2016
事件2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan
持續時間: 24 8月 201626 8月 2016

出版系列

名字RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

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???event.eventtypes.event.conference???2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
國家/地區Taiwan
城市Taipei
期間24/08/1626/08/16

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