A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.