A two-phase fault simulation scheme for sequential circuits

W. C. Wu, C. L. Lee, J. E. Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

A two-phase fault simulation scheme for sequential circuits is proposed. The scheme is done by first performing the true value simulation with several initial patterns and then by performing the fault simulation with the rest of patterns. With the fault simulation approach, some faults which consume much simulation time can be easily and quickly identified and dropped early. As a result, significant speedup on simulation time is obtained. Five cases of faults which cause problems in fault simulation are also discussed.

原文???core.languages.en_GB???
主出版物標題ATS 1993 Proceedings - 2nd Asian Test Symposium
發行者IEEE Computer Society
頁面60-65
頁數6
ISBN(電子)081863930X
DOIs
出版狀態已出版 - 1993
事件2nd IEEE Asian Test Symposium, ATS 1993 - Beijing, China
持續時間: 16 11月 199318 11月 1993

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

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???event.eventtypes.event.conference???2nd IEEE Asian Test Symposium, ATS 1993
國家/地區China
城市Beijing
期間16/11/9318/11/93

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