A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Kuo Hsing Cheng; Chang Chien Hu; Jen Chieh Liu; Hong Yi Huang

doi:10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Kuo Hsing Cheng, Chang Chien Hu, Jen Chieh Liu, Hong Yi Huang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

8 引文斯高帕斯（Scopus）

摘要

This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

原文	???core.languages.en_GB???
主出版物標題	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
頁面	285-288
頁數	4
DOIs	https://doi.org/10.1109/DDECS.2010.5491766
出版狀態	已出版 - 2010
事件	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 - Vienna, Austria 持續時間: 14 4月 2010 → 16 4月 2010

出版系列

名字	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
國家/地區	Austria
城市	Vienna
期間	14/04/10 → 16/04/10

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10.1109/DDECS.2010.5491766

引用此

Cheng, K. H., Hu, C. C., Liu, J. C., & Huang, H. Y. (2010). A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. 於 Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 (頁 285-288). 文章 5491766 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). https://doi.org/10.1109/DDECS.2010.5491766

Cheng, Kuo Hsing ; Hu, Chang Chien ; Liu, Jen Chieh 等. / A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. 頁 285-288 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

@inproceedings{051d6b61364e4caab9422b178b54072f,

title = "A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop",

abstract = "This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.",

keywords = "All digital PLL (ADPLL), Digital controlled oscillator (DCO), Multi-phase, Time-to-digital (TDC)",

author = "Cheng, {Kuo Hsing} and Hu, {Chang Chien} and Liu, {Jen Chieh} and Huang, {Hong Yi}",

year = "2010",

doi = "10.1109/DDECS.2010.5491766",

language = "???core.languages.en_GB???",

isbn = "9781424466139",

series = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",

pages = "285--288",

booktitle = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",

note = "13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 ; Conference date: 14-04-2010 Through 16-04-2010",

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Cheng, KH, Hu, CC, Liu, JC & Huang, HY 2010, A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. 於 Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010., 5491766, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, 頁 285-288, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, 14/04/10. https://doi.org/10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. / Cheng, Kuo Hsing; Hu, Chang Chien; Liu, Jen Chieh 等.
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 285-288 5491766 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

AU - Cheng, Kuo Hsing

AU - Hu, Chang Chien

AU - Liu, Jen Chieh

AU - Huang, Hong Yi

PY - 2010

Y1 - 2010

N2 - This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

AB - This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

KW - All digital PLL (ADPLL)

KW - Digital controlled oscillator (DCO)

KW - Multi-phase

KW - Time-to-digital (TDC)

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Cheng KH, Hu CC, Liu JC, Huang HY. A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. 於 Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 285-288. 5491766. (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). doi: 10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

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