摘要
In this paper, a low-power high-speed static frequency divider is proposed. By utilizing the forward body-bias (FBB) technique and parallel switching topology which employ differential PMOS input pair, the proposed 2:1 static frequency divider can not only be operated at a supply voltage of 0.7V but also keep the structure of tail current source to provide constant current. The frequency divider is designed based on TSMC 0.18μm 1p6m CMOS process. The 2:1 frequency divider can be operated up to maximum operating frequency 10.18 GHz while consuming 1.68 mW from a supply voltage of 0.9V. As operating at supply voltage of 0.7V, the operating frequency is 4.07GHz and the power dissipation is 0.96mW.
原文 | ???core.languages.en_GB??? |
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文章編號 | 4253521 |
頁(從 - 到) | 3848-3851 |
頁數 | 4 |
期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
DOIs | |
出版狀態 | 已出版 - 2007 |
事件 | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States 持續時間: 27 5月 2007 → 30 5月 2007 |