In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.
|出版狀態||已出版 - 2008|
|事件||2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Slovakia|
持續時間: 16 4月 2008 → 18 4月 2008
|???event.eventtypes.event.conference???||2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS|
|期間||16/04/08 → 18/04/08|