@inproceedings{82b20e413c75451f89dbfc1ccae770c6,
title = "A simulator for evaluating redundancy analysis algorithms of repairable embedded memories",
abstract = "We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.",
keywords = "Algorithm design and analysis, Analytical models, Built-in self-test, Circuit faults, Circuit simulation, Circuit testing, Computational modeling, Electrical fault detection, Fault detection, Redundancy",
author = "Huang, {Rei Fu} and Li, {Jin Fu} and Yeh, {Jen Chieh} and Wu, {Cheng Wen}",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; IEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002 ; Conference date: 10-07-2002 Through 12-07-2002",
year = "2002",
doi = "10.1109/MTDT.2002.1029766",
language = "???core.languages.en_GB???",
series = "Records of the IEEE International Workshop on Memory Technology, Design and Testing",
publisher = "IEEE Computer Society",
pages = "68--73",
editor = "Thomas Wik and Bernard Courtois and Yervant Zorian",
booktitle = "Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002",
}