@inproceedings{0136fa5af9334f98b3c4890da596ba89,
title = "A simulator for evaluating redundancy analysis algorithms of repairable embedded memories",
abstract = "We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order improving the accuracy of the analysis results.",
keywords = "embedded memory, memory repair, memory testing, redundancy analysis, simulation",
author = "Huang, {Rei Fu} and Li, {Jin Fu} and Yeh, {Jen Chieh} and Wu, {Cheng Wen}",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 8th IEEE International On-Line Testing Workshop, IOLTW 2002 ; Conference date: 08-07-2002 Through 10-07-2002",
year = "2002",
doi = "10.1109/OLT.2002.1030229",
language = "???core.languages.en_GB???",
series = "Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "262--267",
booktitle = "Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002",
}