A Simple and Flexible Buffer Scheduling in the ATM Switches

In this paper, a simple and high-speed buffer scheduling is proposed. Various classes of cells are identified and belonged to different priority levels in the ATM network. In my proposed buffer scheduling, a physical queue is shared by multiple logical queues belonged to different classes of cells. With my scheduling architecture, simple comparison logic units are cascaded in series to schedule the service among these cells. Shift and comparison mechanisms are employed in the simple comparison logic unit in parallel. In each timeslot, each pair of cells are fed into a simple comparison logic unit; and then compared and exchanged, if necessary, to find their proper places. By cascading comparison logic units, increasing buffer size is simply achieved. Also the comparison logic unit is quite simple and then can operate in real ime; thereby providing high-speed service for real-time connection. Different scheduling for various fields such as priority or survival time can be combined to realize. Therefore, the proposed cell scheduling architecture is not only simple but also provides flexibility.