A scan matrix design for low power scan-based test

Shih Ping Lin, Chung Len Lee, Jwu E. Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the junction mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.

原文???core.languages.en_GB???
主出版物標題Proceedings - 14th Asian Test Symposium, ATS 2005
頁面224-229
頁數6
DOIs
出版狀態已出版 - 2005
事件14th Asian Test Symposium, ATS 2005 - Calcutta, India
持續時間: 18 12月 200521 12月 2005

出版系列

名字Proceedings of the Asian Test Symposium
2005
ISSN(列印)1081-7735

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???14th Asian Test Symposium, ATS 2005
國家/地區India
城市Calcutta
期間18/12/0521/12/05

指紋

深入研究「A scan matrix design for low power scan-based test」主題。共同形成了獨特的指紋。

引用此