A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path

Keyphrases

• Sneak Path 100%
• Resistive Gate 100%
• Freeform 100%
• Energy Efficiency 50%
• Ultrafast 50%
• Two-level 50%
• CMOS Process 50%
• High Activity 50%
• Fin Field-effect Transistor (FinFET) 50%
• Cell Size 50%
• Signal-to-noise 50%
• Data Retention 50%
• Resistive Switching 50%
• 3-bits 50%
• Switching Process 50%
• Programming Current 50%
• Noise Margin 50%
• Comprehensive Reliability 50%
• Process Compatibility 50%
• Active Energy 50%

Engineering

• Resistive 100%
• Operation Level 100%
• Energy Efficiency 33%
• Data Retention 33%
• Noise Margin 33%
• Active High 33%