@inproceedings{df56da703d5648b3993e7f7cd1f6e4c0,
title = "A Reconfigurable Hardware Architecture for Graph Convolution Network in Action Recognition",
abstract = "Graph convolution neural network (GCN) has gained more attention in recent years. Data types like human skeleton joints which are in non-Euclidean space are suitable for GCN. However, due to the high computational complexity and data sparsity of GCN, it is common to have high latency or low power efficiency in CPU or GPU platforms. Therefore, dedicated hardware accelerators are critical for such tasks. In this paper, we proposed a highly parallelized and flexible architecture for the GCN layers of the Spatial-Temporal Graph Convolutional Networks (ST-GCN) model, which is a classic model and widely used in human action recognition. The accelerator also has high scalability due to our proposed method. Compared with the hardware implementation on ST-GCN, the proposed method reduces the latency by up to 39.5% and improves 1.46x on power efficiency.",
keywords = "accelerator, FPGA, graph convolutional neural network, hardware, reconfigurable architecture",
author = "Tsai, {Tsung Han} and Chen, {Tzu Chieh}",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023 ; Conference date: 31-10-2023 Through 03-11-2023",
year = "2023",
doi = "10.1109/APSIPAASC58517.2023.10317398",
language = "???core.languages.en_GB???",
series = "2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1075--1078",
booktitle = "2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023",
}