A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs

Tsu Wei Tseng, Jin Fu Li, Chih Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

30 引文 斯高帕斯(Scopus)

摘要

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512×4×256 design parameters and four memory instances (64×2×32, 128×2×64, 256×4×128, and 512×4×256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512×4×256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%.

原文???core.languages.en_GB???
主出版物標題2006 IEEE International Test Conference, ITC
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)1424402921, 9781424402922
DOIs
出版狀態已出版 - 2006
事件2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
持續時間: 22 10月 200627 10月 2006

出版系列

名字Proceedings - International Test Conference
ISSN(列印)1089-3539

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???event.eventtypes.event.conference???2006 IEEE International Test Conference, ITC
國家/地區United States
城市Santa Clara, CA
期間22/10/0627/10/06

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