A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai; Gung Yu Pan; Hsien Kai Kuo; Jing Yang Jou

doi:10.1109/ASPDAC.2014.6742957

A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai, Gung Yu Pan, Hsien Kai Kuo, Jing Yang Jou

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

6 引文斯高帕斯（Scopus）

摘要

The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

原文	???core.languages.en_GB???
主出版物標題	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
頁面	604-609
頁數	6
DOIs	https://doi.org/10.1109/ASPDAC.2014.6742957
出版狀態	已出版 - 2014
事件	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore 持續時間: 20 1月 2014 → 23 1月 2014

出版系列

名字	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
國家/地區	Singapore
城市	Suntec
期間	20/01/14 → 23/01/14

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10.1109/ASPDAC.2014.6742957

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Lai, C. Y., Pan, G. Y., Kuo, H. K., & Jou, J. Y. (2014). A read-write aware DRAM scheduling for power reduction in multi-core systems. 於 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings (頁 604-609). 文章 6742957 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2014.6742957

@inproceedings{c19cfcd75c4744e283d776dcfa9c5441,

title = "A read-write aware DRAM scheduling for power reduction in multi-core systems",

abstract = "The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.",

author = "Lai, {Chih Yen} and Pan, {Gung Yu} and Kuo, {Hsien Kai} and Jou, {Jing Yang}",

year = "2014",

doi = "10.1109/ASPDAC.2014.6742957",

language = "???core.languages.en_GB???",

isbn = "9781479928163",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "604--609",

booktitle = "2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings",

note = "2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 ; Conference date: 20-01-2014 Through 23-01-2014",

}

Lai, CY, Pan, GY, Kuo, HK & Jou, JY 2014, A read-write aware DRAM scheduling for power reduction in multi-core systems. 於 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings., 6742957, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 頁 604-609, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, Singapore, 20/01/14. https://doi.org/10.1109/ASPDAC.2014.6742957

A read-write aware DRAM scheduling for power reduction in multi-core systems. / Lai, Chih Yen; Pan, Gung Yu; Kuo, Hsien Kai 等.
2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. 2014. p. 604-609 6742957 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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Y1 - 2014

N2 - The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

AB - The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

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SN - 9781479928163

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A read-write aware DRAM scheduling for power reduction in multi-core systems

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