A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai, Gung Yu Pan, Hsien Kai Kuo, Jing Yang Jou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

4 引文 斯高帕斯(Scopus)

摘要

The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

原文???core.languages.en_GB???
主出版物標題2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
頁面604-609
頁數6
DOIs
出版狀態已出版 - 2014
事件2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
持續時間: 20 1月 201423 1月 2014

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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???event.eventtypes.event.conference???2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
國家/地區Singapore
城市Suntec
期間20/01/1423/01/14

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