A programmable online/off-line built-in self-test scheme for RAMs with ECC

Hsing Chen Lu, Jin Fu Li

研究成果: 書貢獻/報告類型會議論文篇章同行評審

4 引文 斯高帕斯(Scopus)

摘要

Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low - only about 2.6% for a 4Kx39-bit SRAM.

原文???core.languages.en_GB???
主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面1997-2000
頁數4
DOIs
出版狀態已出版 - 2009
事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
持續時間: 24 5月 200927 5月 2009

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

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???event.eventtypes.event.conference???2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家/地區Taiwan
城市Taipei
期間24/05/0927/05/09

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