摘要
When operating at a gigahertz-level frequency, a high-frequency signal is distorted and degraded through the channel. To meet the demand of low cost and the low power consumption for consumer electronic products, this paper proposes a power-saving adaptive equalizer with digital-controlled self-slope detection to compensate channel losses. Reducing and shutting down high-speed circuits in addition to digitization are the most effective methods for minimizing both power and cost. This study also proposes a serial processing for reducing one high-speed detection circuit. The main concept is to use a self-slope detection circuit, which compares two continuous serial slopes, instead of a previous detection circuit, which uses a slicer. After compensation, a shutdown mechanism switches OFF the control circuit to reduce power. A serial processing enables channeling the data through the same circuit and path to avoid swing balancing and mismatch problems. An experimental chip was implemented using 90-nm 1P9M CMOS technology. In the experiment, the equalizer is operated at a supply power of 1 V with 4.35 mW. The core area occupies of 120~\mu \text{m} \times 189~\mu \text{m} , and the peak-to-peak jitter measured at 5 Gb/s by using the PRBS31 pattern through a 1.5-m channel is 0.36 UI.
原文 | ???core.languages.en_GB??? |
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頁(從 - 到) | 2097-2108 |
頁數 | 12 |
期刊 | IEEE Transactions on Circuits and Systems I: Regular Papers |
卷 | 65 |
發行號 | 7 |
DOIs | |
出版狀態 | 已出版 - 7月 2018 |