The new proposed phase-locked pulsewidth control loop (PWCL) focus on variable duty cycle of output clock and synchronizes the input clock and output clock. The conventional PWCL can adjust duty cycle but can't synchronize the input and output clocks. By using synchronous mirror delay (SMD) and binary-weighted controlled in charge pump, we can not only achieve the synchronization of the input and output clocks but also vary the duty cycle of the output clock. The HSPICE simulation results are based on TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the proposed PWCL can operate from 250MHz to 400MHz, the duty cycle range of input clock can be operated from 20% to 75%. Moreover, the duty cycle of output clock can be adjusted from 20% to 50% in step of 5%. When the input clock frequency is 250MHz and 400MHz, the power dissipation are 13mW and 20mW, respectively.