A phase-detect synchronous mirror delay for clock skew-compensation circuits

Kuo Hsing Cheng, Chen Lung Wu, Yu Lung Lo, Chia Wei Su

研究成果: 雜誌貢獻會議論文同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new phase-detect synchronous mirror delay (PSMD) circuit is proposed. The PSMD circuit not only can be operated in the narrow pulse clock signal but also can accept the 50% duty-cycle clocks. The conventional SMD can be locked in 2 clock cycle time, but it just can accept only the narrow pulse clock signal. In this proposed PSMD, we have developed a new mirror delay circuits (MCC) which is composed of phase detector (PD). Such a new MCC can provide the proposed PSMD to operate in not only the narrow pulse clock signal, but also 50% duty-cycle clocks, and locked in 2 clock cycle time. The HSPICE simulation results are based on TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the proposed PSMD can be operated from 200MHz to 400MHz and the static phase error is less than 58.7ps. When the input clock frequency is 200MHz and 400MHz, the power dissipation are 6.03mW and 9.87mW, respectively. In addition, the PSMD operation frequency range is depend on the number of delay cells, input buffer and clock drive, the principle can be a template in designing the issue of frequency tuning range in SMD.

原文???core.languages.en_GB???
文章編號1464777
頁(從 - 到)1070-1073
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態已出版 - 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 5月 200526 5月 2005

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