TY - JOUR
T1 - A phase-detect synchronous mirror delay for clock skew-compensation circuits
AU - Cheng, Kuo Hsing
AU - Wu, Chen Lung
AU - Lo, Yu Lung
AU - Su, Chia Wei
PY - 2005
Y1 - 2005
N2 - A new phase-detect synchronous mirror delay (PSMD) circuit is proposed. The PSMD circuit not only can be operated in the narrow pulse clock signal but also can accept the 50% duty-cycle clocks. The conventional SMD can be locked in 2 clock cycle time, but it just can accept only the narrow pulse clock signal. In this proposed PSMD, we have developed a new mirror delay circuits (MCC) which is composed of phase detector (PD). Such a new MCC can provide the proposed PSMD to operate in not only the narrow pulse clock signal, but also 50% duty-cycle clocks, and locked in 2 clock cycle time. The HSPICE simulation results are based on TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the proposed PSMD can be operated from 200MHz to 400MHz and the static phase error is less than 58.7ps. When the input clock frequency is 200MHz and 400MHz, the power dissipation are 6.03mW and 9.87mW, respectively. In addition, the PSMD operation frequency range is depend on the number of delay cells, input buffer and clock drive, the principle can be a template in designing the issue of frequency tuning range in SMD.
AB - A new phase-detect synchronous mirror delay (PSMD) circuit is proposed. The PSMD circuit not only can be operated in the narrow pulse clock signal but also can accept the 50% duty-cycle clocks. The conventional SMD can be locked in 2 clock cycle time, but it just can accept only the narrow pulse clock signal. In this proposed PSMD, we have developed a new mirror delay circuits (MCC) which is composed of phase detector (PD). Such a new MCC can provide the proposed PSMD to operate in not only the narrow pulse clock signal, but also 50% duty-cycle clocks, and locked in 2 clock cycle time. The HSPICE simulation results are based on TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the proposed PSMD can be operated from 200MHz to 400MHz and the static phase error is less than 58.7ps. When the input clock frequency is 200MHz and 400MHz, the power dissipation are 6.03mW and 9.87mW, respectively. In addition, the PSMD operation frequency range is depend on the number of delay cells, input buffer and clock drive, the principle can be a template in designing the issue of frequency tuning range in SMD.
UR - http://www.scopus.com/inward/record.url?scp=49749129376&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1464777
DO - 10.1109/ISCAS.2005.1464777
M3 - 會議論文
AN - SCOPUS:49749129376
SN - 0271-4310
SP - 1070
EP - 1073
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1464777
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -