@inproceedings{905cd2a7220b4d2e89ffbfef90c18df5,
title = "A novel efficient VLSI architecture of 2-d discrete wavelet transform",
abstract = "In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.",
keywords = "Discrete wavelet transform, Lifting",
author = "Hsieh, {Chin Fa} and Tsai, {Tsung Han} and Lai, {Chih Hung} and Shan, {Tai An}",
year = "2008",
doi = "10.1109/IIH-MSP.2008.275",
language = "???core.languages.en_GB???",
isbn = "9780769532783",
series = "Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008",
pages = "647--650",
booktitle = "Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008",
note = "2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008 ; Conference date: 15-08-2008 Through 17-08-2008",
}