@inproceedings{b9d9361ffa304c3f9f850d4ef6c9cb5e,
title = "A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications",
abstract = "A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.",
author = "Hsieh, {E. R.} and Fan, {Y. C.} and Chang, {K. Y.} and Liu, {C. H.} and Chien, {C. H.} and Chung, {Steve S.}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 ; Conference date: 24-04-2017 Through 27-04-2017",
year = "2017",
month = jun,
day = "7",
doi = "10.1109/VLSI-TSA.2017.7942487",
language = "???core.languages.en_GB???",
series = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",
}