@inproceedings{0ba87631cd024420953a805c768edbde,
title = "A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance",
abstract = "In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (> 1012), much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's Vth to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.",
author = "Hsieh, {E. R.} and Chang, {H. Y.} and Chung, {Steve S.} and Chen, {T. P.} and Huang, {S. A.} and Chen, {T. J.} and Osbert Cheng and Wong, {S. Simon}",
note = "Publisher Copyright: {\textcopyright} 2019 The Japan Society of Applied Physics.; 39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
year = "2019",
month = jun,
doi = "10.23919/VLSIT.2019.8776488",
language = "???core.languages.en_GB???",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T138--T139",
booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",
}