TY - JOUR
T1 - A new robust handshake for asymmetric asynchronous micro-pipelines
AU - Cheng, Kuo Hsing
AU - Lee, Yang Han
AU - Chang, Wei Chun
PY - 2003
Y1 - 2003
N2 - In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micropipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 um CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.
AB - In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micropipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 um CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.
UR - http://www.scopus.com/inward/record.url?scp=0038758740&partnerID=8YFLogxK
M3 - 會議論文
AN - SCOPUS:0038758740
SN - 0271-4310
VL - 5
SP - V209-V212
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
Y2 - 25 May 2003 through 28 May 2003
ER -