A new logic synthesis and optimization procedure

K. H. Cheng, V. C. Hsieh

研究成果: 雜誌貢獻會議論文同行評審

摘要

The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

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頁(從 - 到)IV182-IV185
期刊Materials Research Society Symposium - Proceedings
626
出版狀態已出版 - 2001
事件Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
持續時間: 24 4月 200027 4月 2000

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