A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Chih Wen Lu; Chung Len Lee; Jwu E. Chen; Chauchin Su

doi:10.1109/IDDQ.1998.730757

A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Chih Wen Lu, Chung Len Lee, Jwu E. Chen, Chauchin Su

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

3 引文斯高帕斯（Scopus）

摘要

In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.

原文	???core.languages.en_GB???
主出版物標題	Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
編輯	Sankaran M. Menon, Yashwant K. Malaiya
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	0818691913, 9780818691911
DOIs	https://doi.org/10.1109/IDDQ.1998.730757
出版狀態	已出版 - 1998
事件	1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 - San Jose, United States 持續時間: 12 11月 1998 → 13 11月 1998

出版系列

名字	Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
卷	1998-November

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???event.eventtypes.event.conference???	1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
國家/地區	United States
城市	San Jose
期間	12/11/98 → 13/11/98

存取文件

10.1109/IDDQ.1998.730757

引用此

Lu, C. W., Lee, C. L., Chen, J. E., & Su, C. (1998). A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI. 於 S. M. Menon, & Y. K. Malaiya (編輯), Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 文章 730757 (Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998; 卷 1998-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IDDQ.1998.730757

Lu, Chih Wen ; Lee, Chung Len ; Chen, Jwu E. 等. / A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI. Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998. 編輯 / Sankaran M. Menon ; Yashwant K. Malaiya. Institute of Electrical and Electronics Engineers Inc., 1998. (Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998).

@inproceedings{ce02da7eb9f24ec4891df9c2ad1e647e,

title = "A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI",

abstract = "In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.",

author = "Lu, {Chih Wen} and Lee, {Chung Len} and Chen, {Jwu E.} and Chauchin Su",

note = "Publisher Copyright: {\textcopyright} 1998 IEEE.; 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 ; Conference date: 12-11-1998 Through 13-11-1998",

year = "1998",

doi = "10.1109/IDDQ.1998.730757",

language = "???core.languages.en_GB???",

series = "Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Menon, {Sankaran M.} and Malaiya, {Yashwant K.}",

booktitle = "Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998",

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Lu, CW, Lee, CL, Chen, JE & Su, C 1998, A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI. 於 SM Menon & YK Malaiya (編輯), Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998., 730757, Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998, 卷 1998-November, Institute of Electrical and Electronics Engineers Inc., 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998, San Jose, United States, 12/11/98. https://doi.org/10.1109/IDDQ.1998.730757

A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI. / Lu, Chih Wen; Lee, Chung Len; Chen, Jwu E. 等.
Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998. 編輯 / Sankaran M. Menon; Yashwant K. Malaiya. Institute of Electrical and Electronics Engineers Inc., 1998. 730757 (Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998; 卷 1998-November).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

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AU - Lu, Chih Wen

AU - Lee, Chung Len

AU - Chen, Jwu E.

AU - Su, Chauchin

PY - 1998

Y1 - 1998

N2 - In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.

AB - In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.

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M3 - 會議論文篇章

AN - SCOPUS:79951684156

T3 - Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

BT - Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

A2 - Menon, Sankaran M.

A2 - Malaiya, Yashwant K.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

Y2 - 12 November 1998 through 13 November 1998

ER -

Lu CW, Lee CL, Chen JE, Su C. A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI. 於 Menon SM, Malaiya YK, 編輯, Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998. Institute of Electrical and Electronics Engineers Inc. 1998. 730757. (Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998). doi: 10.1109/IDDQ.1998.730757

A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

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