A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Guan Xun Chen; Chung Len Lee; Jwu E. Chen

A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Guan Xun Chen, Chung Len Lee, Jwu E. Chen

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

6 引文斯高帕斯（Scopus）

摘要

In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.

原文	???core.languages.en_GB???
頁（從 - 到）	58-61
頁數	4
期刊	Proceedings of the Asian Test Symposium
出版狀態	已出版 - 2004
事件	Proceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan 持續時間: 15 11月 2004 → 17 11月 2004

引用此

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A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

摘要

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引用此