A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

Kuo Hsing Cheng, Yu Lung Lo, Wen Fang Yu, Shu Yin Hung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.

原文???core.languages.en_GB???
主出版物標題Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
編輯Yehya Ismail, Wael Badawy
發行者Institute of Electrical and Electronics Engineers Inc.
頁面90-93
頁數4
ISBN(電子)076951944X, 9780769519449
DOIs
出版狀態已出版 - 2003
事件3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 - Calgary, Canada
持續時間: 30 6月 20032 7月 2003

出版系列

名字Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
國家/地區Canada
城市Calgary
期間30/06/032/07/03

指紋

深入研究「A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation」主題。共同形成了獨特的指紋。

引用此