A memory-reduced Log-MAP kernel for turbo decoder

Tsung Han Tsai; Cheng Hung Lin; An Yeu Wu

doi:10.1109/ISCAS.2005.1464767

A memory-reduced Log-MAP kernel for turbo decoder

Tsung Han Tsai, Cheng Hung Lin, An Yeu Wu

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

9 引文斯高帕斯（Scopus）

摘要

Generally, the Log-MAP kernel of the turbo decoding consume large memories in hardware implementtation. In this paper, we propose a new Log-MAP kernel to reduce memory usage. The comparison result shows our proposed architecture can reduce the memory size to 26% of the classical architecture. We also simplify the memory data access in this kernel design without extra address generaters. For 3GPP standard, a prototyping chip of the turbo decoder is implemented to verify the proposed memory-reduced Log- MAP kernel in 3.04×3.04mm2 core area in UMC 0.18um CMOS process.

原文	???core.languages.en_GB???
文章編號	1464767
頁（從 - 到）	1032-1035
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464767
出版狀態	已出版 - 2005
事件	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan 持續時間: 23 5月 2005 → 26 5月 2005

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10.1109/ISCAS.2005.1464767

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AB - Generally, the Log-MAP kernel of the turbo decoding consume large memories in hardware implementtation. In this paper, we propose a new Log-MAP kernel to reduce memory usage. The comparison result shows our proposed architecture can reduce the memory size to 26% of the classical architecture. We also simplify the memory data access in this kernel design without extra address generaters. For 3GPP standard, a prototyping chip of the turbo decoder is implemented to verify the proposed memory-reduced Log- MAP kernel in 3.04×3.04mm2 core area in UMC 0.18um CMOS process.

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A memory-reduced Log-MAP kernel for turbo decoder

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