A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS

Keyphrases

• Low Power 100%
• Area-efficient 100%
• Static Random Access Memory 100%
• Read Stability 100%
• Transistor 16%
• Memory Cell 16%
• Power Consumption 16%
• Power Source 16%
• CMOS Process 16%
• Power Efficiency 16%
• Aspect Ratio 16%
• Power Efficient 16%
• Power Supply 16%
• Bitline 16%
• Read Operation 16%
• Conventional Architecture 16%
• Memory Architecture 16%
• Read Static Noise Margin 16%
• Direct Connection 16%
• Inverter Circuit 16%
• Efficient Operation 16%
• Pre-charge 16%
• Conventional Counterpart 16%
• Write Cycle 16%
• Memory Circuits 16%
• Cell Area 16%

Engineering

• Random Access Memory 100%
• Power Supply 16%
• Electric Power Utilization 16%
• Nodes 16%
• Similarities 16%
• Bit Line 16%
• Direct Connection 16%
• Noise Margin 16%
• Cell Area 16%
• Aspect Ratio 16%
• Inverter 16%