摘要
In this paper, a low power digital intermediate frequency (IF)-discriminator is proposed. A lower frequency reference clock 10kHz is used as the reference frequency in this new IF-discriminator circuit. This new structure utilizes a 4-bit residual-code counter and register to distinguish the difference of input signal frequency. HSPICE simulation result shows that the tolerance margin of the new IF-discriminator for frequency variation is improved effectively.
原文 | ???core.languages.en_GB??? |
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主出版物標題 | Recent Advances in Circuits, Systems and Signal Processing |
發行者 | World Scientific and Engineering Academy and Society |
頁面 | 111-113 |
頁數 | 3 |
ISBN(列印) | 9608052645 |
出版狀態 | 已出版 - 2002 |