A low power all digital IF-discriminator design

Kuo Hsing Cheng, Ta Wei Liu, Yung Hsiang Lin, Jiann Chyi Rau

研究成果: 書貢獻/報告類型篇章同行評審

摘要

In this paper, a low power digital intermediate frequency (IF)-discriminator is proposed. A lower frequency reference clock 10kHz is used as the reference frequency in this new IF-discriminator circuit. This new structure utilizes a 4-bit residual-code counter and register to distinguish the difference of input signal frequency. HSPICE simulation result shows that the tolerance margin of the new IF-discriminator for frequency variation is improved effectively.

原文???core.languages.en_GB???
主出版物標題Recent Advances in Circuits, Systems and Signal Processing
發行者World Scientific and Engineering Academy and Society
頁面111-113
頁數3
ISBN(列印)9608052645
出版狀態已出版 - 2002

指紋

深入研究「A low power all digital IF-discriminator design」主題。共同形成了獨特的指紋。

引用此