A Low Power 16 Gbps CTLE and Quarter-Rate DFE with Single Adaptive System

This article presents a low-power 16-Gbps equalizer with a single adaptive system. A novel equalizer architecture relaxes the timing constraint of decision feedback equalizer (DFE) from one period to two periods. Thus, we are able utilize low-power techniques to realize DFE to reach better power efficiency. The data path is composed of a continuous time linear equalizer (CTLE) and 2-tap DFE. To achieve a lower bit error rate (BER), sign-sign least-mean-square (SS-LMS) algorithm is adopted to provide an optimum gain of CTLE and tap weight of DFE simultaneously. This chip is fabricated with TSMC 90 nm (TN90GUTM)1P9M CMOS process and occupies an active area of 0.047 mm2. The proposed adaptive equalizer can compensate for the channel loss up to 16 dB at 16 Gb/s. The power consumption is 4.24 mW from 1.0V supply, and achieves the figure of merit of 0.265mW/Gbps and 0.0165 mW/dB/Gbps.