A low jitter self-calibration PLL for 10Gbps SoC transmission links application

Kuo Hsing Cheng; Yu Chang Tsai; Kai Wei Hong; Yen Hsueh Wu

doi:10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application

Kuo Hsing Cheng, Yu Chang Tsai, Kai Wei Hong, Yen Hsueh Wu

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm².

原文	???core.languages.en_GB???
主出版物標題	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
頁面	786-789
頁數	4
DOIs	https://doi.org/10.1109/ICECS.2008.4674971
出版狀態	已出版 - 2008
事件	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta 持續時間: 31 8月 2008 → 3 9月 2008

出版系列

名字	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
國家/地區	Malta
城市	St. Julian's
期間	31/08/08 → 3/09/08

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10.1109/ICECS.2008.4674971

引用此

Cheng, K. H., Tsai, Y. C., Hong, K. W., & Wu, Y. H. (2008). A low jitter self-calibration PLL for 10Gbps SoC transmission links application. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (頁 786-789). 文章 4674971 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674971

@inproceedings{53fb40ae197148c690f2aaed17151b5e,

title = "A low jitter self-calibration PLL for 10Gbps SoC transmission links application",

abstract = "A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm2.",

author = "Cheng, {Kuo Hsing} and Tsai, {Yu Chang} and Hong, {Kai Wei} and Wu, {Yen Hsueh}",

year = "2008",

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isbn = "9781424421824",

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pages = "786--789",

booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

note = "15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 ; Conference date: 31-08-2008 Through 03-09-2008",

}

Cheng, KH, Tsai, YC, Hong, KW & Wu, YH 2008, A low jitter self-calibration PLL for 10Gbps SoC transmission links application. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4674971, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 頁 786-789, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application. / Cheng, Kuo Hsing; Tsai, Yu Chang; Hong, Kai Wei 等.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 786-789 4674971 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AB - A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm2.

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Cheng KH, Tsai YC, Hong KW, Wu YH. A low jitter self-calibration PLL for 10Gbps SoC transmission links application. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 786-789. 4674971. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application

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