A low jitter self-calibration PLL for 10-Gbps SoC transmission links application

Kuo Hsing Cheng, Yu Chang Tsai, Chien Nan Jimmy Liu, Kai Wei Hong, Chin Cheng Kuo

研究成果: 雜誌貢獻期刊論文同行評審

摘要

A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low K VCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-μm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm 2.

原文???core.languages.en_GB???
頁(從 - 到)964-972
頁數9
期刊IEICE Transactions on Electronics
E92-C
發行號7
DOIs
出版狀態已出版 - 2009

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