In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the variations. A modified theoretical model of the sub-harmonically injection-locked PLL with self-aligned injection is developed for the design methodology. The in-band phase noise of the sub-harmonically injection-locked PLL can be significantly improved using the self-aligned sub-harmonically injection-locked technique. The design considerations of the locking range, loop bandwidth, and frequency division ratio are addressed. At 10 GHz, the measured phase noise of the proposed PLL with self-aligned injection at 1-MHz offset is-130.2 dBc/Hz with a root-mean-square jitter of 44 fs. The total dc power consumption is 62.7 mW. From 10̂C to 70̂C, the measured phase noise at 1-MHz offset and jitter are better than-129 dBc/Hz and 48 fs, respectively. This work demonstrates excellent performance and good robustness over the variations, and it can be compared to the previously reported state-of-the-art sub-harmonically injection-locked PLLs.
|頁（從 - 到）||543-555|
|期刊||IEEE Transactions on Microwave Theory and Techniques|
|出版狀態||已出版 - 3月 2014|