A low jitter delay-locked-loop applied for DDR4

This work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the de-velopment and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6 Gbps - 3.2 Gbps. The stability of clock becomes an essential part of design. This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90 nm technology with a nominal supply voltage 1.2 V and I/O supply voltage 2.5 V. The input frequency is at 1.6 GHz. Peak to peak jitter is 12.33 ps and RMS jitter is 1.66 ps. The power dissipation of DLL is 15.6 mW and chip area is 0.047 mm².