每年專案
摘要
In this paper, a control logic-reduced memory addressing scheme with a modified arithmetic processing unit (PE) for memory-based fast Fourier transform (FFT) is presented. The proposed scheme supports the conflict-free memory accessing and continuous-flow (CF) FFT operation. Furthermore, the timing delay is independent of FFT length and the circuit area is minimized in the proposed address generator. A case study of radix-4 256-point CF-FFT is analyzed. The comparison results synthesized with 90nm CMOS technology show that the hardware complexity is significantly reduced. Therefore, the proposed addressing scheme is suitable for high radix algorithm and long FFT length applications.
原文 | ???core.languages.en_GB??? |
---|---|
主出版物標題 | 2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
發行者 | Institute of Electrical and Electronics Engineers Inc. |
頁面 | 502-505 |
頁數 | 4 |
ISBN(列印) | 9781538663509 |
DOIs | |
出版狀態 | 已出版 - 11 9月 2018 |
事件 | 3rd International Conference on Computer and Communication Systems, ICCCS 2018 - Nagoya, Japan 持續時間: 27 4月 2018 → 30 4月 2018 |
出版系列
名字 | 2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
---|
???event.eventtypes.event.conference???
???event.eventtypes.event.conference??? | 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
---|---|
國家/地區 | Japan |
城市 | Nagoya |
期間 | 27/04/18 → 30/04/18 |
指紋
深入研究「A Low-Complexity Generalized Memory Addressing Scheme for Continuous-Flow Fast Fourier Transform」主題。共同形成了獨特的指紋。專案
- 1 已完成