A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET

We introduce one kind of embedded dynamic-random-access-memory (eDRAM) array (16 kilo-bits) with peripheral circuits. Each cell in an array comprises 1-control-Fin-type-field-effect-transistor [FinFET (T)] and 1-storage-npn-diode (D). The latter can be implemented by a nFinFET with the floating gate electrode. This 1T1D eDRAM technology is fully integrated with the 16-nm FinFET process and can be continually shrunk to the 3-nm technology node. The size of the unit-cell is 0.0242μ m 2. This 1T1D eDRAM cell can be programmed by the Zener-tunneling mechanism with 0.8 V of a writing voltage in 8 ns; the reading can be accomplished in 7 ns at -0.2 V. 116∼μ s of data retention at 25°C ( 101∼μ s at 75°C); 100∼μ W of the write power; 9.125∼μ W of the read power have been recorded as well. These experimental pieces of evidence suggest that our 1T1D embedded DRAM technology could replace the conventional 1-transistor-1-capacitance (1T1C) eDRAM one with better cost-efficiency and lower power in the advanced CMOS technology to 3-nm node.