A loading effect insensitive and high precision clock synchronization circuit

Kai Wei Hong, Kuo Hsing Cheng, Chi Hsiang Chen, Jen Chieh Liu, Chien Cheng Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

2 引文 斯高帕斯(Scopus)

摘要

This study proposes a output loading effect insensitive and high precision clock synchronization (HPCS) circuit which can accept variable duty cycle clock signal. This HPCS is capable of synchronizing the external clock and the internal clock in 3 clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control circuit, the HPCS operates correctly with an arbitrary duty cycle (25% ∼ 75%) clock signal. Second, the HPCS works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Finally, the HPCS can enhance the resolution between the external clock and internal clock with a fine tuning structure. After phase locking, the maximum static phase error is less than 20 ps. The proposed chip is fabricated in a TSMC 130 nm CMOS process, and has an operating frequency range from 300 MHz to 600 MHz. At 600 MHz, the power consumption and rms jitter are 2.4 mW and 3.06 ps, respectively. The active area of this chip is 0.3x0.13 mm2.

原文???core.languages.en_GB???
主出版物標題ESSCIRC 2010 - 36th European Solid State Circuits Conference
頁面514-517
頁數4
DOIs
出版狀態已出版 - 2010
事件36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
持續時間: 14 9月 201016 9月 2010

出版系列

名字ESSCIRC 2010 - 36th European Solid State Circuits Conference

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???event.eventtypes.event.conference???36th European Solid State Circuits Conference, ESSCIRC 2010
國家/地區Spain
城市Sevilla
期間14/09/1016/09/10

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