A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yun Chao Yu, Chih Sheng Hou, Li Jung Chang, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

研究成果: 書貢獻/報告類型會議論文篇章同行評審

6 引文 斯高帕斯(Scopus)

摘要

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

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主出版物標題Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs
出版狀態已出版 - 2013
事件2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
持續時間: 29 4月 20131 5月 2013

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

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???event.eventtypes.event.conference???2013 IEEE 31st VLSI Test Symposium, VTS 2013
國家/地區United States
城市Berkeley, CA
期間29/04/131/05/13

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