A hybrid built-in self-test scheme for DRAMs

Chi Chun Yang; Jin Fu Li; Yun Chao Yu; Kuan Te Wu; Chih Yen Lo; Chao Hsun Chen; Jenn Shiang Lai; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/VLSI-DAT.2015.7114502

A hybrid built-in self-test scheme for DRAMs

Chi Chun Yang, Jin Fu Li, Yun Chao Yu, Kuan Te Wu, Chih Yen Lo, Chao Hsun Chen, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

6 引文斯高帕斯（Scopus）

摘要

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

原文	???core.languages.en_GB???
主出版物標題	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114502
出版狀態	已出版 - 28 5月 2015
事件	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan 持續時間: 27 4月 2015 → 29 4月 2015

出版系列

名字	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家/地區	Taiwan
城市	Hsinchu
期間	27/04/15 → 29/04/15

存取文件

10.1109/VLSI-DAT.2015.7114502

引用此

Yang, C. C., Li, J. F., Yu, Y. C., Wu, K. T., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., & Chou, Y. F. (2015). A hybrid built-in self-test scheme for DRAMs. 於 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 文章 7114502 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114502

@inproceedings{5477a45043624625950a71b7698bed5d,

title = "A hybrid built-in self-test scheme for DRAMs",

abstract = "This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.",

author = "Yang, {Chi Chun} and Li, {Jin Fu} and Yu, {Yun Chao} and Wu, {Kuan Te} and Lo, {Chih Yen} and Chen, {Chao Hsun} and Lai, {Jenn Shiang} and Kwai, {Ding Ming} and Chou, {Yung Fa}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114502",

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series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

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Yang, CC, Li, JF, Yu, YC, Wu, KT, Lo, CY, Chen, CH, Lai, JS, Kwai, DM & Chou, YF 2015, A hybrid built-in self-test scheme for DRAMs. 於 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114502, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114502

A hybrid built-in self-test scheme for DRAMs. / Yang, Chi Chun; Li, Jin Fu; Yu, Yun Chao 等.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114502 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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T1 - A hybrid built-in self-test scheme for DRAMs

AU - Yang, Chi Chun

AU - Li, Jin Fu

AU - Yu, Yun Chao

AU - Wu, Kuan Te

AU - Lo, Chih Yen

AU - Chen, Chao Hsun

AU - Lai, Jenn Shiang

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

AB - This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

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T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Y2 - 27 April 2015 through 29 April 2015

ER -

A hybrid built-in self-test scheme for DRAMs

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