This study proposes a high precision fast locking arbitrary duty cycle clock synchronization (HPCS) circuit. This HPCS is capable of synchronizing the external clock and the internal clock in three clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control circuit, the HPCS operates correctly with an arbitrary duty cycle (25%-75%) clock signal. Second, the HPCS works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Finally, the HPCS can enhance the resolution between the external clock and internal clock with a fine tuning structure. After phase locking, the maximum static phase error is less than 20 ps. The proposed chip is fabricated in a TSMC 130-nm CMOS process, and has an operating frequency range from 300 to 600 MHz. At 600 MHz, the power consumption and rms jitter are 2.4 mW and 3.06 ps, respectively. The active area of this chip is 0.3 × 0.13 mm 2.
|頁（從 - 到）||1218-1228|
|期刊||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|出版狀態||已出版 - 7月 2011|