A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

Kuo Hsing Cheng; Cia Wei Su; Kai Fei Chang; Cheng Liang Hung; Wei Bin Yang

doi:10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

Kuo Hsing Cheng, Cia Wei Su, Kai Fei Chang, Cheng Liang Hung, Wei Bin Yang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

5 引文斯高帕斯（Scopus）

摘要

In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

原文	???core.languages.en_GB???
主出版物標題	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
頁面	178-181
頁數	4
DOIs	https://doi.org/10.1109/ESSCIR.2006.307560
出版狀態	已出版 - 2006
事件	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Switzerland 持續時間: 19 9月 2006 → 21 9月 2006

出版系列

名字	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
國家/地區	Switzerland
城市	Montreux
期間	19/09/06 → 21/09/06

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10.1109/ESSCIR.2006.307560

引用此

Cheng, K. H., Su, C. W., Chang, K. F., Hung, C. L., & Yang, W. B. (2006). A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. 於 ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (頁 178-181). 文章 4099733 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2006.307560

@inproceedings{15b28e54765848a8870a43e4b87bce73,

title = "A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation",

abstract = "In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.",

author = "Cheng, {Kuo Hsing} and Su, {Cia Wei} and Chang, {Kai Fei} and Hung, {Cheng Liang} and Yang, {Wei Bin}",

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isbn = "1424403022",

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pages = "178--181",

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note = "ESSCIRC 2006 - 32nd European Solid-State Circuits Conference ; Conference date: 19-09-2006 Through 21-09-2006",

}

Cheng, KH, Su, CW, Chang, KF, Hung, CL & Yang, WB 2006, A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. 於 ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference., 4099733, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, 頁 178-181, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, Montreux, Switzerland, 19/09/06. https://doi.org/10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. / Cheng, Kuo Hsing; Su, Cia Wei; Chang, Kai Fei 等.
ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 178-181 4099733 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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T1 - A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

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AU - Su, Cia Wei

AU - Chang, Kai Fei

AU - Hung, Cheng Liang

AU - Yang, Wei Bin

PY - 2006

Y1 - 2006

N2 - In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

AB - In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

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Cheng KH, Su CW, Chang KF, Hung CL, Yang WB. A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. 於 ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 178-181. 4099733. (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). doi: 10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

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