A hierarchical test scheme for system-on-chip designs

Jin Fu Li, Hsin Jung Huang, Jeng Bin Chen, Chih Ping Su, Cheng Wen Wu, Chuang Cheng, Shao I. Chen, Chi Yi Hwang, Hsiao Ping Lin

研究成果: 雜誌貢獻會議論文同行評審

9 引文 斯高帕斯(Scopus)


System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test anti lest access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area anti pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

頁(從 - 到)486-490
期刊Proceedings -Design, Automation and Test in Europe, DATE
出版狀態已出版 - 2002
事件2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
持續時間: 4 3月 20028 3月 2002


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