A generalized conflict-free memory addressing scheme for continuous-flow parallel-processing FFT processors with rescheduling

Keyphrases

• Addressing Scheme 25%
• Arithmetic Computation 25%
• Configurability 25%
• Conflict-free 100%
• Continuous Flow 100%
• Continuous Flow Operation 25%
• Fast Fourier Transform 100%
• Flow Variables 25%
• Hardware Complexity 25%
• Hardware Efficiency 25%
• High Efficiency 25%
• High Utilization 25%
• High-radix 50%
• Memory Access 25%
• Memory Requirements 25%
• Memory Scheme 100%
• Memory-based 50%
• Multipath Delay Commutator 25%
• Parallel Arithmetic 25%
• Parallel Processing 100%
• Processing Operations 25%
• Processing Unit 50%
• Radix 25%
• Radix-2 25%
• Radix-4 25%
• Shared Memory 25%
• Twiddle Factor 25%

Computer Science

• Addressing Scheme 100%
• Computation Cycle 25%
• Configurability 25%
• Continuous Flow 100%
• Fast Fourier Transform 100%
• Flow Operation 25%
• Free Memory 100%
• Memory Access 25%
• Multipath Delay 25%
• Parallel Processing 100%
• Processing Unit 50%
• radix 2 25%
• radix-4 25%
• Shared Memory Requirement 25%