A DFT for semi-DC fault diagnosis for switched-capacitor circuits

Sheng Jer Kuo; Chung Len Lee; Soon Jyh Chang; Jwu E. Chen

doi:10.1109/ETW.1999.804228

A DFT for semi-DC fault diagnosis for switched-capacitor circuits

Sheng Jer Kuo, Chung Len Lee, Soon Jyh Chang, Jwu E. Chen

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

In this paper, a design-for testability (DFT) technique is presented to diagnose switched-capacitor (SC) circuits. In order to avoid the effect that pure DC signal cannot pass through un-switched capacitors, we use semi-DC signal to diagnose SC circuits. Furthermore, we propose a controllable opamp that it can be controlled to normal mode or test mode. In normal mode, it passes signal normally; in test mode, it provides a semi-DC test signal (VDD or VSS) and blocks the signals from the stage before controlled stage. In our diagnosis method, we consider faults both in capacitors and in opamps. Experiments have carried out to verify the practicality of this technique.

原文	???core.languages.en_GB???
主出版物標題	Proceedings - European Test Workshop 1999, ETW 1999
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	58-63
頁數	6
ISBN（電子）	076950390X, 9780769503905
DOIs	https://doi.org/10.1109/ETW.1999.804228
出版狀態	已出版 - 1999
事件	1999 European Test Workshop, ETW 1999 - Constance, Germany 持續時間: 25 5月 1999 → 28 5月 1999

出版系列

名字	Proceedings - European Test Workshop 1999, ETW 1999

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	1999 European Test Workshop, ETW 1999
國家/地區	Germany
城市	Constance
期間	25/05/99 → 28/05/99

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10.1109/ETW.1999.804228

引用此

@inproceedings{b477381b1b0c4c6a88680e43abf18992,

title = "A DFT for semi-DC fault diagnosis for switched-capacitor circuits",

abstract = "In this paper, a design-for testability (DFT) technique is presented to diagnose switched-capacitor (SC) circuits. In order to avoid the effect that pure DC signal cannot pass through un-switched capacitors, we use semi-DC signal to diagnose SC circuits. Furthermore, we propose a controllable opamp that it can be controlled to normal mode or test mode. In normal mode, it passes signal normally; in test mode, it provides a semi-DC test signal (VDD or VSS) and blocks the signals from the stage before controlled stage. In our diagnosis method, we consider faults both in capacitors and in opamps. Experiments have carried out to verify the practicality of this technique.",

author = "Kuo, {Sheng Jer} and Lee, {Chung Len} and Chang, {Soon Jyh} and Chen, {Jwu E.}",

year = "1999",

doi = "10.1109/ETW.1999.804228",

language = "???core.languages.en_GB???",

series = "Proceedings - European Test Workshop 1999, ETW 1999",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "58--63",

booktitle = "Proceedings - European Test Workshop 1999, ETW 1999",

note = "1999 European Test Workshop, ETW 1999 ; Conference date: 25-05-1999 Through 28-05-1999",

}

Kuo, SJ, Lee, CL, Chang, SJ & Chen, JE 1999, A DFT for semi-DC fault diagnosis for switched-capacitor circuits. 於 Proceedings - European Test Workshop 1999, ETW 1999., 804228, Proceedings - European Test Workshop 1999, ETW 1999, Institute of Electrical and Electronics Engineers Inc., 頁 58-63, 1999 European Test Workshop, ETW 1999, Constance, Germany, 25/05/99. https://doi.org/10.1109/ETW.1999.804228

A DFT for semi-DC fault diagnosis for switched-capacitor circuits. / Kuo, Sheng Jer; Lee, Chung Len; Chang, Soon Jyh 等.
Proceedings - European Test Workshop 1999, ETW 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 58-63 804228 (Proceedings - European Test Workshop 1999, ETW 1999).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AU - Kuo, Sheng Jer

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N2 - In this paper, a design-for testability (DFT) technique is presented to diagnose switched-capacitor (SC) circuits. In order to avoid the effect that pure DC signal cannot pass through un-switched capacitors, we use semi-DC signal to diagnose SC circuits. Furthermore, we propose a controllable opamp that it can be controlled to normal mode or test mode. In normal mode, it passes signal normally; in test mode, it provides a semi-DC test signal (VDD or VSS) and blocks the signals from the stage before controlled stage. In our diagnosis method, we consider faults both in capacitors and in opamps. Experiments have carried out to verify the practicality of this technique.

AB - In this paper, a design-for testability (DFT) technique is presented to diagnose switched-capacitor (SC) circuits. In order to avoid the effect that pure DC signal cannot pass through un-switched capacitors, we use semi-DC signal to diagnose SC circuits. Furthermore, we propose a controllable opamp that it can be controlled to normal mode or test mode. In normal mode, it passes signal normally; in test mode, it provides a semi-DC test signal (VDD or VSS) and blocks the signals from the stage before controlled stage. In our diagnosis method, we consider faults both in capacitors and in opamps. Experiments have carried out to verify the practicality of this technique.

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BT - Proceedings - European Test Workshop 1999, ETW 1999

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1999 European Test Workshop, ETW 1999

Y2 - 25 May 1999 through 28 May 1999

ER -

A DFT for semi-DC fault diagnosis for switched-capacitor circuits

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