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## 摘要

In this paper, an input-decimation technique for the recursive discrete Fourier transform (RDFT)/inverse DFT (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is worth noting that the input-decimation approach is presented to decrease the number of input sequences for the recursive filter so that the computation cycle of RDFT/RIDFT can be shortened to meet the computing time requirement (3.6μs) for the high-speed broadband communication systems. Therefore, the input-decimation RDFT/RIDFT algorithm is able to carry out at least 55.5% reduction of the total computation cycles compared with the considered algorithms. Furthermore, holding the advantages of input-decimation technique, the computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. The area and the power consumption can be minimized by employing the cost-efficient constant multiplier with the refined signed-digit expression of twiddle factors. Finally, the physical implementation results show that the core area is 0.37× 0.37 mm^{2} with 0.18μ m CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of computational efficiency per unit area (CEUA) and really outperform the previous works.

原文 | ???core.languages.en_GB??? |
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文章編號 | 8822601 |

頁（從 - 到） | 4713-4726 |

頁數 | 14 |

期刊 | IEEE Transactions on Circuits and Systems I: Regular Papers |

卷 | 66 |

發行號 | 12 |

DOIs | |

出版狀態 | 已出版 - 12月 2019 |

## 指紋

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