A comparison of fault injection experiments under different verification environments

The main work of this paper is to characterize the dependability of fault-tolerant systems by using two different hardware design environments (SystemC and VHDL). For SystemC, we inject errors into the components' outputs, whereas faults into the inside of components for VHDL. The difference of the simulation results between SystemC and VHDL is discussed thoroughly through observing two parameters: one is the probability of a fault causing an effective error and another is the relationship between fault duration and error duration. The above two parameters dominate the discrepancy between the two different platforms. The experimental results show the effect of the parameters on the error coverage. This study can promote the fault-tolerant design and verification environment to a higher abstraction level.