A CMOS VCO for IV, 1GHz PLL applications

Kuo Hsing Cheng, Ching Wen Lai, Yu Lung Lo

研究成果: 書貢獻/報告類型會議論文篇章同行評審

13 引文 斯高帕斯(Scopus)

摘要

This paper describes a 1V, 1GHz low-noise phase locked- loop (PLL) using a noise-rejected voltage-controlled ring oscillator (VCO). In order to improve the power consumption and oscillation frequency of the PLL, we design the VCO with a new structure of the delay cell. This VCO consists of four-stage fully differential delay cells with the pre-charged scheme that can obtain the characteristics of high speed and low voltage operation. And the bias generator circuit can increase the tuning range and tuning linearity of VCO. The HSPICE simulation results are based upon TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the VCO can operate from 50 to 1100 MHz, and when the input control voltage is 0.6V, the oscillation frequency is 1GHz. The power consumption of the PLL is 1.092mW at a supply voltage of 1V.

原文???core.languages.en_GB???
主出版物標題Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
頁面150-153
頁數4
出版狀態已出版 - 2004
事件Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
持續時間: 4 8月 20045 8月 2004

出版系列

名字Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

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???event.eventtypes.event.conference???Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
國家/地區Japan
城市Fukuoka
期間4/08/045/08/04

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