A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

E. R. Hsieh, C. M. Hung, T. Y. Wang, Steve S. Chung, R. M. Huang, C. T. Tsai, T. R. Yew

研究成果: 書貢獻/報告類型會議論文篇章同行評審

2 引文 斯高帕斯(Scopus)

摘要

Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

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主出版物標題2014 IEEE International Electron Devices Meeting, IEDM 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面12.2.1-12.2.4
版本February
ISBN(電子)9781479980017
DOIs
出版狀態已出版 - 20 2月 2015
事件2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
持續時間: 15 12月 201417 12月 2014

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
號碼February
2015-February
ISSN(列印)0163-1918

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???event.eventtypes.event.conference???2014 60th IEEE International Electron Devices Meeting, IEDM 2014
國家/地區United States
城市San Francisco
期間15/12/1417/12/14

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